Verification
L2 · Structured
Risk
Low
Health
Active
Trust
Silver
What it doesAI
Open-source AI agent flow converting natural language specs to Verilog RTL and UVM verification, enabling front-end signoff on EDA tools.
- Converts natural language specs to Verilog RTL
- Automates UVM verification and signoff
- Integrates with commercial EDA tools
AI-generated from the repo README — for reference only.
Installation
dsh plugin --profile web add github:chipweaver/veripowerInstall method: GitHub · no verification record (L1-L5)
Compatibility
| DSH Version | Status |
|---|---|
| not stated | no verification record |
Requirements
- • Node.js: not stated
- • DSH: not stated
- • External credentials: none detected
Security Report
Automated static scan, not manual review.
DSH.SO VETPASSEDa3bf9a
Security reviewAutomated review · daily
PASSED
Vet static analysis found no suspicious behavior — verdict is clean.
0 critical·0 high·0 medium·100 score
plugin version
0.1.9dsh manifestscanned commit
a3bf9a74a9b22026-08-25latest commit
a3bf9a74a9b2vet verdict
clean · gitscore 100Vet is an AST static scan (npm artifact or git source).
`[](https://www.dsh.so/artifact/veripower/)`Disclaimer: automated static analysis, not a security guarantee. Always review what you install.
Risk details
No critical or warning findings.
Activity
Last commit 2026-08-25 · activity: Active
• Repo created: 2026-08-25
• Stars: ★ 4 · Forks: 1
• Health: Active — committed within last 30 days
Source
GitHub: github.com/chipweaver/veripower
